Quadrature clocking schemes are widely used in modern communications systems, but often suffer from phase imbalance. The initial clock phases are typically generated by a central phase locked loop (PLL), but, during the routing and distribution process, the in-phase (I) and quadrature (Q) phases may become misaligned, particularly if the phases are provided across chip to multiple locations. Quadrature skew can be a phase deviation between the I and Q clocks from the ideal 90°, and quadrature skew is typically caused by the propagation time difference of the I and Q signals transmitting through corresponding channels. Differences in conductor length, trace geometry, via stubs, loading, buffer mismatch, supply differences and some other factors introduce quadrature skew. As the period of the clock decreases, quadrature skew is expected to become more pronounced. Additionally, duty cycle distortion can also be present. Quadrature skew and duty cycle distortion increase random and deterministic jitter and degrade the eye of a receiver.
There have been some attempts to solve problems associated with quadrature skew and duty cycle distortion, and, in FIG. 1, an example of a conventional clocking scheme or system 100 can be seen. Here, transmitter 102 transmits a clock signal CLK over a transmission medium 104 to a polyphase circuit 106 (which is adjacent to or “close to” a receiver 108). The polyphase circuit 106 can then generate the I (PH1 and PH3) and Q (PH2 and PH4) signals locally so as to avoid the quadrature skew and duty cycle distortion, which can occur by transmission these signals PH1 to PH4 over long transmission lines (i.e., 104). A problem with this system 100, however, is that the polyphase circuit 106 is generally comprised of PLLs and/or delay locked loops (DLLs) or other circuits, which can occupy a large amount of area and can consume a substantial amount of power. Therefore, there is a need for an improved clocking scheme or system.
Some other conventional circuits are: U.S. Pat. No. 6,084,452; U.S. Pat. No. 6,819,728; U.S. Pat. No. 6,933,759; and U.S. Patent Pre-Grant Publ. No. 2002/0085658.